09: 03 PM EDT – The last discussion of Hot Chips 31 is from Microsoft, that will certainly be raising the cover of the silicon behind its HoloLens 2.0 item.

09: 17 PM EDT – Here we go

09: 17 PM EDT – HPU 2.0

09: 18 PM EDT – Holographic cpu

09: 18 PM EDT – Custom silicon, clearly

09: 19 PM EDT – This audio speaker has actually been educated. There are deliberate stops when she details things

09: 20 PM EDT – Application cpu runs the application, and also the HPU changes the provided photo and also sends out to the display screen

09: 20 PM EDT – HPU works with particular work

09: 21 PM EDT – Takes the aesthetic hints and also enables the HPU to track where the hands go to perpetuity

09: 21 PM EDT – 79 mm2 on TSMC 16 FF+

09: 21 PM EDT – 123 M gateways, 2B transistors

09: 22 PM EDT – 2016 Tapeout

09: 22 PM EDT – 125 Mb of SRAM

09: 22 PM EDT – First model

09: 22 PM EDT – First model headset *

09: 23 PM EDT – HPU 2 is devoted to just Microsoft work

09: 23 PM EDT – Targets a solitary Microsoft RTOS

09: 23 PM EDT – No MMUs, basic disrupts

09: 23 PM EDT – Frees up the equipment

09: 23 PM EDT – Works with the software application group to set up caches and also memory

09: 24 PM EDT – Balance in between specialized HW calculate and also adaptability/ programmability

09: 24 PM EDT – SIMD Fixed Point at top

09: 24 PM EDT – Does 2D handling

09: 24 PM EDT – FVP, Floating Vector Processor on base, does 3D

09: 24 PM EDT – 2 Tensiilica cpus per node

09: 24 PM EDT – Trade off location for latency – reduced latency was crucial

09: 24 PM EDT – DMA network per core

09: 25 PM EDT – New deepness based formulas

09: 25 PM EDT – 13 statically designated calculate cores

09: 25 PM EDT – >> 1 TOP of programmable calculate

09: 25 PM EDT – 100 s of tailored guidelines

09: 26 PM EDT – Algorithm profiling to transform 10 s of ops right into a solitary guideline

09: 27 PM EDT – Example, boxavg_2x16 x8 is a solitary cycle guideline

09: 27 PM EDT – guideline is put on every pixel, conserving 10 k+ cycles per structure

09: 27 PM EDT – Hardened calculate on ToF sensing unit

09: 27 PM EDT – JBL filter

09: 28 PM EDT – Uses 3 sensing units and also uses filter

09: 28 PM EDT – But really did not fit on the node. But readjusted a C design right into RTL, for equipment. Reduces power to 1/3, and also 1/30 th latency

09: 29 PM EDT – Now thermals

09: 30 PM EDT – Power gating, clock gating, eliminating ULV cells

09: 31 PM EDT – Most electronic reasoning at 250 MHz, calculate at 500 MHz

09: 31 PM EDT – Reduced voltage, Vmin

09: 31 PM EDT – DVFS per chip

09: 32 PM EDT – Could take the guard bands off

09: 32 PM EDT – Can lower the power by 20%

09: 32 PM EDT – at Vmin

09: 32 PM EDT – Now system combination

09: 33 PM EDT – HPU ahead, App cpu in back

09: 33 PM EDT – PCIe 2.0 x1 at 100 MB/s comms in between front and also back

09: 34 PM EDT – Rendered photos returned by means of MIPI to HPU

09: 34 PM EDT – MIPI QoS prices

09: 35 PM EDT – 6.8 GB/s required to sync right into 2 lanes of LPDDR4

09: 35 PM EDT – Custom DRAM scheduler on HPU 2.0

09: 36 PM EDT – Hologram security

09: 37 PM EDT – Multiple posture updates per structure

09: 37 PM EDT – Hardened block on HPU decouples the provide resolution to show resolution

09: 37 PM EDT – Gives a lot more thermal clearance to GPU

09: 38 PM EDT – HPU Timestamps the sensing unit information as it is available in

09: 38 PM EDT – Hardened semantic network

09: 39 PM EDT – Q&A

09: 40 PM EDT – Q: Comment on deepness video camera? A: Custom ToF, there’s a great deal of literary works out.

09: 40 PM EDT – Q: Scheduler? A: Statically designated formulas to the calculate devices

09: 41 PM EDT – Q: Transfer information in between various VFPs? A: Small quantity of transmission capacity in between VFPs, yet primarily in between memory.

09: 43 PM EDT – That’s a cover! Thank you for sticking with us via all the Hot Chips protection!


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